S. SISKOS and S.VLASSIS I. PITAS

Laboratory of Electronics, Department of Physics

Department of Informatics

Aristotle University of Thessaloniki, 54006 Thessaloniki, Greece.

ABSTRACT: An analog implementation of an order-statistics filter based on current-mode techniques is presented in this paper. The circuit is designed using switched-current delay lines and current maximum extractors. These filters could be easily incorporated to smart sensors as well as to smart cameras. SPICE simulation results demonstrate the feasibility of simple analog filters using current-mode techniques.

In the recent years the use of non-linear filters has exhibited a strong growth due to their capabilities to cope with system nonlinearities, non-Gaussian noise environments and sensor and perceptual system nonlinearities. These filters find applications in the telecommunications, radar, sonar, remote sensing, geophysical signal processing, image processing and computer vision [1]. Numerous digital implementations have been proposed in the literature. During the last years, analog implementation has gained new interest due to its high processing speed and silicon area efficiency, since there is no need of A/D and D/A converters. However, there are only a few publications on analog realisations [2-6] and two recent current-mode designs of analog median filters [7,8] .

One of the most frequently used classes of non-linear filters is based on order statistics [9]. Let us suppose that the input samples in the filter window are denoted by where k is the time index. If we order them according to their magnitude, we get their order statistics: . The minimal input sample is and the maximal input sample is . The j-th order sample is denoted by , 1£ j £ n. An L-filter based on order statistics produces the output

where the a_j are constants.

The median filter, the order statistics filter, the moving average filter, the α-trimmed filter [1,9] and erosion and dilation (max/min filters) [10] are special cases of the L-filter by an appropriate choice of filter coefficients. Dispersion measures [9], which can be used as scale estimators or edge detectors, can be considered as special case of (1), e.g. range or quasi-range edge detectors. In the following we shall concentrate our efforts in proposing digital filter architectures that are suitable to order statistics filtering and that are easily implemented in a hybrid (analog/digital) way. The proposed architectures are essentially suited to one dimensional signal filtering (e.g sound, smart sensors, smart cameras, ECG/EEGS, measurements).

2. THE CURRENT-MODE ORDER STATISTICS FILTERS: STRUCTURE AND OPERATION

The current-mode order statistics filter structure is shown in fig. 1. It includes four basic elements: a voltage-to-current converter (V/I), a current mode delay, a winner-take-all circuit (WTA) and a AB class weighted current mirror (WCM).

The V/I contains the transistors M₁, M₂ which operate in the saturation and in the linear region respectively and have the same aspect W/L. The output current of the V/I is given by the following equation [11]:

where V_X is the input voltage, m is equal to V_SS+V_T, k is the transconductance parameter and V_T is the threshold voltage of transistor M₁, M₂. Taking into account the first order terms of the Taylor series expansion of eq.(2) around zero. It is obtained a linear relation between I_V/I and V_X , given by:

The output currents of the V/I's will feed a multiple-input current maximum selector through the delay line "delay1". This is the basic Winner-Take-All (WTA) circuit which is formed by transistor pairs M_1i, M_2i one pair for each input current and a current sink formed by transistor M_O [12]. This circuit selects at its output the maximum current between the input currents. Due to the DC offset current (the first term of eq.(3), for V_X =0) of the input currents Ix_i , the WTA circuit operates both for positive and for negative signals. The output current of the WTA feeds the delay line "delay2". Since the WTA is fed in a parallel manner it is needed to sample and hold the input signal. For this propose we use the "delay1" delay line. Also in order to sort the currents provided in serial manner at the output of the maximum selector, clock delay circuit is needed to sample the signal and to synchronize the data in the structure. The recently proposed switched-currents (SI) technique is used to implemented the delay elements. In our case a more complicated current delay line based on SI delay cells free of clock feedthrough described in [13], is used to synchronize the operations of the comparison elements.

The AB class weighted current mirrors are based on a wide-band push-pull current amplifier [14]. It is possible to change the weights of the current mirrors digitally by adding or subtracting transistors from an array of transistors or by using special digitally controlled current mirror structures [15].

In the following, we shall describe how these elements are put together to form the entire current mode order statistics filters. The upper part of the filter performs the sorting operation. The input signals V_X are converted to currents and after a delay time (due to the delay line) these currents feed the WTA circuit. The WTA output provides a current corresponding to the maximum input voltage.

The basic WTA circuit has been modified by adding inverters Inv_i (i=1,2...n), one inverter for each pair of transistors, in order to obtain information about which is the maximum input. Each inverter drives a latch F-F_i which controls a switch SW_i. If the current Ix_q (1£ q£ n) corresponding to the input X_q is the maximum current, the voltage V_dq at the drain of the q-th transistor M_2q will be positive corresponding at the «high» logic level (logic "1") while all voltages at the drains, Vd_{i,(iΉ q)} will be close to V_SS since transistors M_{2i,(iΉ q)} operate in the triode region [12]. Thus, this current is the output current of the WTA circuit. Therefore, the Inv_q output will be «low» (logic "0") and the inverters Inv_{i,(iΉ q)} outputs will be high (logic "1").

At the beginning of the sorting operation all switches are closed and all currents Ix_i feed the WTA circuit. The inverter output Inv_q of the maximum current Ix_q is «low» and the others are «high». After one clock period the F-F_q open the switch SW_q and the q-th input is disabled from the filter structure. All the other switches are closed so the rest of the (n-1) currents Ix_{i,(iΉ q)} are fed to WTA circuit yet. The circuit continues to select the second highest value and so on, until the classification of all signal values into a descending order.

Since each selected output current contains an offset current, a voltage-to-current converter V/I_offset is put at the output of the sorting circuit in order to subtract this offset current. This subtraction permits to avoid the multiplication of the offset current with the weights a_j at the second part of the structure. Therefore, the selected currents are pipelined into the SI delay line «delay2» (fig.1).

After a delay time all signals are forwarded in a parallel manner to the weighted current mirrors and they are summed to produce the sum of the weighted currents. This total current is converted to a voltage using a current-to-voltage converter (I/V) which has the same structure with V/I. At the I/V converter an offset current (provided by a V/I_offset converter) is fed in order to provide the right value of the output voltage. This voltage is the sum of the weighted input voltages, thus producing the output of an order-statistics filter, according to eq.(1).

This structure could also provide the second or the third highest value. When the delay line «delay2» is filled by the sorted signal values, it is obvious that a supplementary current mirror to the second, for example, delay element may provide the second highest value separately by appropriate clocking, without disturbing the functionality of the order-statistics filter.

SPICE simulations have been performed in order to verify the performance of the proposed circuit, using MIETEC CMOS 2m m parameters and supply voltage Vsupply=± 2.5V. Transistor sizes for the V/I converter is (W/L)_M1.2=3/20 and for the current maximum circuit were

(W/L)_M1i =(W/L)_M2i =3/3μm .

The distortion is less than 1% for the operating range ± 1V. The sampling period is 500KHz and the window size equal to 5. The estimated area of the circuit is approximately 0.1 mm² and the power consumption is 14mW.

In order to improve the accuracy and the output resistance and to minimize systematic errors of current mirrors, cascode current mirror, large transistor areas and currents can be employed. It should be noted that the effect of spikes on circuit performance, due to the switches feedthrough, are minimal because dummy switches were used for the simulations.

Fig. 2 shows the simulation results of the whole circuit for 5 inputs (n=5) with a_j=1, j=1,..,5. From eq.(1) for a_j=1 the output signal y_k is the sum of five inputs: . Fig. 3 shows the a-trimmed filter output: . The output of the filter is the average of the three median inputs. Fig.4 shows the edge detector filter output. The output of the filter is the difference between fifth and first input: .

The proposed structure may be implemented for a higher number of inputs by using appropriate number of delay line and comparison elements. The number of inputs is practically limited only by the transfer accuracy of the delayed signal.

An analog current-mode implementation of a generalised order-statistics filter is presented in this work. The filter may provide also the median, the moving average, an L-filter as well as the a-trimmed mean filter. These filters could be easily incorporated to smart sensors as well as to smart cameras.

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Fig. 1 The current-mode order statistics filter implementation

Fig. 2 Input and output waveforms. The output is the sum of the inputs :

Fig. 3 Input and output waveforms for the a-trimmed filter. The output is :

Fig. 4 Input and output waveforms. The output is the range edge detector :