S. SISKOS and S. VLASSIS

Laboratory of Electronics, Department of Physics

Aristotle University of Thessaloniki

I. PITAS

Department of Informatics

Aristotle University of Thessaloniki

An analog implementation of running min/max filters based on current-mode techniques is presented in this paper. Switched-current delay cells and current/voltage two inputs min/max selectors are used either for current or voltage inputs respectively.

The voltage two input min/max circuit is designed using current conveyors and a modified structure of this is used to implement the running min/max filter for window size n=8.

Simulation results demonstrate the feasibility of the proposed implementation, which can be extended to a higher window size.

Fast structures for running max/min filtering

The problem of running max/min filtering can be formulated as follows. Let by an one-dimensional signal. The output of a max or min filter is given by :

(1)

where n is the filter length (window size) and T is the max or min operator respectively. (1) is called " running" max or min filtering because after each output calculation, the filter window is shifted one position to the right (i.e. it "runs").

The computational complexity, measured in number of comparisons per output point, is C(n)=n-1. It is desirable to construct filter structures that have a smaller number of comparisons per output point in order to speed the filtering process. This is accomplished by employing the "divide-and-conquer" strategy.

Let as suppose that the filter window size n is a power of two : 2=2^k. It is easily seen that max or min calculation of n numbers can be split into the max or min calculation of two subsequences of length n/2 each:

(2)

This procedure can be repeated recursively until we reach subsequences of length 2 [4]. In this case, the max or min calculation of two numbers is done by one comparison only. The corresponding flow diagram is shown in Figure 1 for n=8. Each dot corresponds to one comparison . The flow diagram has stages. Only one extra comparison per output point is needed at each stage. Therefore, the computational complexity of this structure is reduced to , which is much less than the complexity n-1 of the classical max or min computation. Therefore, the proposed algorithm is clearly superior than the classical approach.

This recursive algorithm for calculating the max or min is described by:

(3)

where:

(4)

Equation (3) describes formally a very efficient filter structure for calculating the running max/min filtering that is shown in Figure 2 for n=8 [4]. This structure requires n-1 registers for storing the intermediate results comparators. Its throughput delay is given by:

(5)

where T_C is the time required for one comparison. This architecture can be easily implemented digitally for digital signal processing. However, it can also be implemented in an analog way provided that analog delay lines as well as analog comparators are available.

During the last years, analog implementation has gained new interest due to its high processing speed and silicon area efficiency, since there is no need of A/D and D/A converters. For sorting operations, numerous digital implementations have been proposed. However, there are few publications on analog realisations [5-9] and two recent current-mode designs of analog median filters [10,11].

Current-mode approach is recently recognised as a very powerful design technique to implement functions, since current-mode circuits present high operating speed, high resolution, wide dynamic range and low supply voltage requirements.

Furthermore, as a result of the simple configuration and the current mode operation, standard CMOS process can be used in actual implementation, thus making mixed-signal processing possible.

In the following, we shall concentrate on the analog implementation of the structure shown in Figure 2. We shall first provide SPICE simulations of current conveyor based analog min/max comparators. Subsequently, we shall simulate the performance of the overall analog structure, considering that the input signals might be either voltages or currents.

A comparison element is the fountamental block of any sorting network. The comparison elements used in this implementation are simple two input current-mode min/max selector circuits.

The current-mode current maximum selector is shown in Fig. 3a. This is a basic Winner-take-all circuit based on the interconnection of two cells. Each cell contain the transistors M₁₁-M₁₂ and M₂₁-M₂₂ [12]. The result of the competition of these two cells connected by the gate of transistor M₁₁ and M₂₁, is a shared gate voltage corresponding to the saturation value imposed by the maximum input current. This circuit provides a maximum current sink output, which is transformed to a current source and then duplicated by using appropriate current mirroring.

The current minimum selector, shown in fig. 3b, is based on a modified circuit of the previous maximum selector. The min operation is related to the max operation by De Morgan’s law [13]:

The voltage min/max selector is based on the well known current-mode building blocs, the second generation current conveyors (CCII).

The input voltages of the proposed circuit are converted into currents and the previously described two-input current minimum/maximum circuit selects the minimum/maximum current. This current is converted into an output voltage which corresponds to the maximum or the minimum input voltage depending on the type of the current selector used.

In the following, we shall introduce the current conveyor building block and we shall describe the maximum selector. A corresponding configuration represents the minimum one selector.

The current mode circuit which has gained most acceptance as an extremely versatile building block is the second generation current conveyor (CCII) [14]. The CCII is a three port building block which can be operated with both current and voltage signals at the input, providing a current signal at the output. It performs two follower operation modes, voltage and current: V_X=V_Y and I_Z =± I_X (Fig. 4). Therefore, when a voltage is applied at node Y, a current proportional to that voltage is drawn the node X and an equal current is conveyed at node Z through the current follower mode.

Fig. 5 shows the implementation of maximum selector for two-input voltages. The high input impedance, input Y of each CCII+, serves as the voltage input of the maximum operator. The current flowing at the Z terminals of the two input CCII+ feeds the current maximum selector circuit. The output current feeds the X terminal of another CCII+ functioning in a current follower configuration (V_Y=0). The maximum selected voltage will appear at the Z terminal of this current conveyor. It is obvious that the value of the resistance at node X of each CCII can adjust the gain and, consequently, the value of the output current.

Since filtering of serial input data involves sampling the input periodically, a clock delay circuit is needed to sample the signal and to synchronise the data flow in the structure.

The recently proposed switched-currents (SI) technique is used to implement the delay element. SI technique requires no special analog process options, no operational amplifiers, it is prone to take advantage of advanced digital design and offers the possibility of resolution levels beyond those achievable with component matching. The MOS transistor is used as a sampling device (memory), thus making the SI analog-sampled-data a robust implementation technique. The basic switched-current delay element is shown in Fig. 6. In our case a current delay line, based on SI delay cell free of clock feedthrough described in [15], is used to synchronise the operations of the comparison elements. It should be noted that, in order to improve the performance of this circuit, cascoded current mirrors and dummy switches were used for the SPICE simulations. By appropriate current mirroring, the output current feeds the next comparison element.

The overall structure of the running min/max filter (CRF) is implemented for current inputs using the previously described building blocs. In the case of voltage inputs a modified current conveyor with two identical outputs is used at the input of the filter (CRF) in order to convert the voltages into currents. A current conveyor is put at the output to convert the output current to the corresponding maximum output voltage functioning in the current follower mode as shown in Fig. 7.

Simulations results for the two input max current selector are depicted in Fig.8. The input signals are triangular waveforms with frequency of 500KHz. It may be observed that the transitions are sharp. The error of I_out at the transition points was less than 0.6% of the full scale value (FS) and 0.2% FS at the other points for the max circuit. The accuracy of the current max operator is the same as that of a Wilson current mirror, which presents an output impedance about 100 times than a simple current mirror. In order to improve accuracy and minimise random errors typical of current mirrors, large transistor areas and currents can be employed [16]. Corresponding results have been shown simulations for the min circuit.

Simulation results for the voltage maximum circuit are similar as in the case of current inputs. In this case the current conveyor used has been described in [14]. The accuracy in the transition points is less than 1% and the operating range of this circuit is ñ 2.2V for ñ 2.5V of supply voltages. The frequency of operation of the above described circuits is in the range of 1MHz.

Fig. 9a shows the simulation results of the whole circuit CRF for ranning max calculation, for window size n=8 and frequency of sampling 1MHz. For fast simulation purposes and to demonstrate feasibility, the simulations were performed using a model for the current delay line. The output signal y_i corresponds to the maximum signal between the 8 samples of the input x_i, x_i-1, ... x_i-7. The FS error is less than 1% and the power consumption is about 14mW.

Simulation results for voltage inputs shown in Fig. 9b, are similar with these ones for current inputs. The reduction of the spikes due to the clock feedthrough, are minimal because dummy switches are used for the simulations of the delay line.

The proposed structure can be used for higher window size than n=8 by cascading appropriate number of delay lines and comparison elements. The window size is practically limited only by the transfer accuracy of the delayed signal.

In this work an analog implementation of a min/max circuit is presented, using switched current delay cells and current-mode comparison elements. The circuit is designed for current inputs using current min/max extractors.

A two input current conveyor based min/max operator is presented for the case of voltage inputs demonstrating high accuracy. This structure is modified in the case of the implementation of the running min/max filter for window size n=8, in order to avoid successive voltage-to-current and current-to-voltage conversions which might deteriorate the performance of the filter. The proposed circuit may operate at frequency of 1MHz.

It is demonstrated that switched current cells coupled with current-mode building blocks are very suitable to construct externally fast, simple and affordable filters that operate directly on the analog signal and can be easily incorporated to smart sensors as well as into smart cameras.

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Fig.1. The max calculation flow diagram for n=8.

Fig. 2. The running max/min filter structure for window size n=8.

Fig. 3. The current maximum selector (a), and minimum selector (b) circuits.

Fig. 4. The block diagram of a current conveyor.

Fig. 5. The two-input voltage maximum circuit.

Fig. 6. The basic delay switched current element.

Fig. 7. The overall structure for voltage inputs.

Fig. 8. Maximum I_out selection of two input voltages I₁,I₂.

Fig. 9. Simulation results for the running max filter n=8 for current (a) and voltage (b) inputs.